1. Field of the Invention
The present invention relates to a semiconductor memory device, and particularly to a twin-cell DRAM (Dynamic Random Access Memory) storing one bit of data by two memory cells. More particularly, the invention relates to a memory cell structure of a DRAM, which is formed of twin-cell structures and has improved refresh characteristics.
2. Description of the Background Art
For example, Japanese Patent Laying-Open No. 7-130172, which will be referred to as a “prior art 1” hereinafter, has disclosed a twin-cell DRAM storing one bit of data by two memory cells for suppressing lowering of an operation margin such as lowering of a read voltage, which may occur in memory cells having a reduced layout area.
In the prior art 1, a layout of memory cells is similar to that of general DRAM cells storing one bit of data by one cell (i.e., in a single mode). Two word lines are simultaneously selected, and data of memory cell is read onto each bit line of bit line pair. In this twin-cell DRAM storing complementary data in the two memory cells, it is possible to double a voltage difference between the bit lines, as compared with the DRAM of the one-bit/one-cell type (i.e., the single cell type), so that the sense operation can be stable.
FIG. 17 shows an array structure of a conventional twin-cell DRAM in the prior art.
In the twin-cell DRAM, as shown in FIG. 17, a twin-cell unit 101, which is a storage unit for one bit data, is formed of two DRAM cells 100 connected to complementary bit lines BL and /BL forming a bit line pair BLP, respectively. The two word lines related to DRAM cells 100, which form the same twin-cell unit, form a word line pair WLP. For example, word lines WL and WL# in FIG. 17 form a word line pair WLP, and are commonly (i.e., simultaneously) selected.
DRAM cell 100 has a select (access) transistor 110 connected between corresponding bit line BL (or /BL) and a storage node 140 as well as a capacitor 120 connected between a cell plate 130 and storage node 140. Access transistor 110 and bit line BL (or /BL) are electrically connected via a bit line contact 160, and storage node 140 and access transistor 110 are electrically connected via a storage node contact 170.
As already described, DRAM cell 100 stores data in the form of electric charges accumulated on storage node 140 by capacitor 120. Cell plate 130 is provided commonly to the whole memory cell array, and is fixed at a predetermined cell plate voltage VCP.
A sense amplifier 105 amplifies a voltage difference between complementary bit lines BL and /BL forming the bit line pair to a difference equal to that between a power supply voltage Vdd and a ground voltage GND. Two DRAM cells 100 forming the same twin-cell unit 101 bear data at complementary levels (i.e., H- and L-levels), respectively.
FIG. 18 illustrates a behavior of voltages on the bit line pair, which is exhibited when power supply voltage Vdd is used as a precharge voltage of bit lines.
Referring to FIG. 18, each of the complementary bit lines is precharged to power supply voltage Vdd before selection of the word line at a time T1. When word line WL thus precharged is selected and activated to attain H-level, a voltage change ΔV in the negative direction corresponding to the L-level data necessarily occurs on one of the complementary bit lines. Through an amplifying operation of the sense amplifier between times T2 and T3, a voltage difference ranging from power supply voltage Vdd to ground voltage GND can be generated between the complementary bit lines forming bit line pair BLP.
As illustrated in FIG. 19, therefore, a refresh time tREF2 in the twin-cell DRAM is defined by a time, which elapses before the voltage on the storage node storing H-level data (i.e., the storage node set to power supply voltage Vdd) lowers to ground voltage GND corresponding to the voltage on the storage node storing L-level data.
In the DRAM cell, since a capacitor is used as a data record medium, the stored data may disappear due to a leak current. For preventing this disappearance of data, as described before, the DRAM internally reads and rewrites the memory cell data to perform a refresh operation for restoring original data.
As the memory cell is miniaturized to a higher extent, an electrostatic capacity value of the memory cell capacitor decreases, and thereby the refreshing must be performed at shorter intervals. In general, the DRAM cannot be accessed during the refresh operation. Therefore, the shorter refresh interval lowers the processing efficiency of the system. Further, a power consumption for the refreshing increases.
In the general twin-cell DRAM disclosed in the prior art 1 or the like, the refresh interval can be longer than that in the single-cell DRAM. In recent years, however, semiconductor devices have been employed in an increasing number of portable devices primarily powered by batteries, and therefore demands for reduction of the size and power consumption of the semiconductor memory devices have been increasing. Thus, the twin-cell DRAM is likewise required to increase further the refresh period, and thus to improve further the refresh characteristics.
Further, in the twin-cell DRAM, since one bit of data is stored in two memory cells, a cell unit storing one bit of data necessarily occupies a large area. If two layouts of the conventional DRAM cells are used for achieving the twin-cell unit storing one bit of the data, the layout area of the twin-cell unit forming the data storage unit increases double. In this case, the storage capacity decreases to half the capacity of the single-cell DRAM of the one-bit/one-cell type, and it becomes difficult to achieve a twin-cell DRAM of a large storage capacity.